FPGA Cyclone IV - Conector VGA

/*
Learn the principle of VGA display, display color bar signal.
Connect the VGA port of the development board and the computer monitor.
DIP switch 1, 2 at the same time not on the dial, then display 8-color square (checkerboard grid)
If dip switch 1 is up and 2 is not up, the 8-color checkerboard will be displayed in different directions.
If dip switch 1 and 2 are turned ON at the same time, an 8-color horizontal bar is displayed.
If DIP switch 1 is not toggled and 2 is toggled ON, 8-color vertical bars are displayed.
*/

module VGA(
   clock,
   switch,
   disp_RGB,
   hsync,
   vsync
);

input  clock;     // System Input Clock 50MHz
input  [1:0]switch;
output [2:0]disp_RGB;    // VGA data output
output  hsync;     //VGA line synchronization signal
output  vsync;     //VGA Field Synchronization Signal

reg [9:0] hcount;  // VGA Line Scan Counter
reg [9:0] vcount;  // VGA Field Scan Counter
reg [2:0] data;
reg [2:0] h_dat;
reg [2:0] v_dat;

// reg [9:0] timer;

reg   flag;
wire  hcount_ov;
wire  vcount_ov;
wire  dat_act;
wire  hsync;
wire   vsync;
reg  vga_clk;

// VGA Line and Field Scan Timing Parameter Table
parameter hsync_end   = 10'd95,
   hdat_begin = 10'd143,
   hdat_end = 10'd783,
   hpixel_end = 10'd799,
   vsync_end = 10'd1,
   vdat_begin = 10'd34,
   vdat_end = 10'd514,
   vline_end = 10'd524;

always @(posedge clock)
begin
 vga_clk = ~vga_clk;
end

//************************VGA driver section******************************* 
//line scan
always @(posedge vga_clk)
begin
 if (hcount_ov)
  hcount <= 10'd0;
 else
  hcount <= hcount + 10'd1;
end
assign hcount_ov = (hcount == hpixel_end);
// field scan
always @(posedge vga_clk)
begin
 if (hcount_ov)
 begin
  if (vcount_ov)
   vcount <= 10'd0;
  else
   vcount <= vcount + 10'd1;
 end
end

assign  vcount_ov = (vcount == vline_end);

assign dat_act =    ((hcount >= hdat_begin) && (hcount < hdat_end))
     && ((vcount >= vdat_begin) && (vcount < vdat_end));
assign hsync = (hcount > hsync_end);
assign vsync = (vcount > vsync_end);
assign disp_RGB = (dat_act) ?  data : 3'h00;
      

//************************Display data processing section******************************* 
//Picture display delay counter
/*always @(posedge vga_clk)
begin
 flag <= vcount_ov;
 if(vcount_ov && ~flag)
  timer <= timer + 1'b1;
end
*/

always @(posedge vga_clk)
begin
 case(switch[1:0])
  2'd0: data <= h_dat;     // Selection of horizontal color strips
  2'd1: data <= v_dat;     // Select Vertical Colored Stripes
  2'd2: data <= (v_dat ^ h_dat); // Generate a checkerboard grid
  2'd3: data <= (v_dat ~^ h_dat); // Generate a checkerboard grid
 endcase
end

always @(posedge vga_clk)  // vertical bar
begin
 if(hcount < 223)
  v_dat <= 3'h7;   // white
 else if(hcount < 303)
  v_dat <= 3'h6;   // cian
 else if(hcount < 383)
  v_dat <= 3'h5;   // magenta
 else if(hcount < 463)
  v_dat <= 3'h4;   // blue
 else if(hcount < 543)
  v_dat <= 3'h3;   // yellow
 else if(hcount < 623)
  v_dat <= 3'h2;   // green
 else if(hcount < 703)
  v_dat <= 3'h1;   // red
 else 
  v_dat <= 3'h0;   // black
end

always @(posedge vga_clk) // multicolored stripes
begin
 if(vcount < 94)
  h_dat <= 3'h7;   // white
 else if(vcount < 154)
  h_dat <= 3'h6;   // cian
 else if(vcount < 214)
  h_dat <= 3'h5;   // magenta
 else if(vcount < 274)
  h_dat <= 3'h4;   // blue
 else if(vcount < 334)
  h_dat <= 3'h3;   // yellow
 else if(vcount < 394)
  h_dat <= 3'h2;   // green
 else if(vcount < 454)
  h_dat <= 3'h1;   // red
 else 
  h_dat <= 3'h0;   // black
end

endmodule